Workshop on Hybrid Multi-core Computing
Held in conjunction with HiPC 2011
Bangalore, December 18, 2011
(Click here to for a report on WHMC-2010 and program details)
Abstract: It is clear that near future will see an exponential increase in the number of cores on a chip, as well as in heterogeneity of cores available for a computation. Memory and processing capabilities are organized in complex hierarchies in such systems. Strong NUMA factors further complicate programming. It has been argued that we need a multi-level programming methodology to match this. I argue that addition of a new degree of freedom, an adaptive runtime system, significantly simplifies the parallel programming problem. I wil draw upon our research to illustrate how one can free the programmer from much of the the burden of dealing with the heterogeneity and hierarchy by employing a relatively flat model consisting of interacting objects, aided by a runtime system that can move objects and computations around, among nodes, and among cores and accelerators within a node. Examples will include Computational astronomy, biomolecular simulations, and KD-trees.
- Paper Session - 2
Matthieu Ospici, Dimitri Komatitsch, Jean-François Méhaut and Thierry Deutsch. SGPU 2: a runtime system for using large applications on clusters of hybrid nodes
Yuhong Zhang, Md. Mostofa Ali Patwary, Sanchit Misra, Ankit Agrawal, Wei-Keng Liao and Alok Choudhary. Enhancing Parallelism of Pairwise Statistical Significance Estimation for Local Sequence Alignment (slides)
- 1530 - HPC in India: Academia
4 @ 5 minutes each: R Govindarajan (IISc), Srinivas Aluru (IITB),
Subodh Kumar (IITD), Kishore Kothapalli (IIIT-H).
1600 - Break
- 1630 - HPC in India: Industry
6 @ 5 minutes each: Infosys, CRL, IBM IRL, GE, MSR, CDAC
Santonu Sarkar (Infosys), Vipin Chaudhary (CRL), Jyothish Soman (IRL),
Srihari Narasimhan (GE), Sarat Chandra Babu (CDAC), Kaushik Rajan (MSR).
- 1700 - Panel Discussion: "Multi and Manycore computing in the Future"
Vipin Chaudhary, R Govindarajan, John Owens, Ming Lin (UNC)
Moderator: P J Narayanan
- 1800 - Wrapup and Thanks followed by posters in parallel with a social event with food hosted by Nvidia India
List of Posters
- Tavish Vaidya and Prof. Sharat Chandran (IIT-B)
- 1830 - End
- Matthieu Ospici, Dimitri Komatitsch, Jean-François Méhaut and Thierry Deutsch. SGPU 2: a runtime system for using large applications on clusters of hybrid nodes
- Yuhong Zhang, Md. Mostofa Ali Patwary, Sanchit Misra, Ankit Agrawal, Wei-Keng Liao and Alok Choudhary. Enhancing Parallelism of Pairwise Statistical Significance Estimation for Local Sequence Alignment
- Erich Marth and Siegfried Benkner. Language Support for Pipelined Applications on Heterogeneous Many-Core Architectures
- Jens Breitbart. Programming hybrid systems with implicit memory based synchronization
CALL FOR PAPERS
The second Workshop on Hybrid Multi-core Computing will be held in conjunction with the 18th International Conference on High Performance Computing (HiPC) being held at Bangalore, India. The workshop will focus on algorithmic, applied, and analytical issues in hybrid multi-core computing. The workshop aims at bringing together researchers and practitioners in the rapidly evolving area of hybrid multi-core computing. Hybrid multi-core computing uses a mix of CPUs and special purpose accelerators to arrive at highly efficient, practical, and scalable solutions. This raises several important issues including the mechanism(s) to execute concurrently on a hybrid computing platform.
The workshop will focus on issues emerging out of hybrid multi-core computing. The workshop shall feature invited talk(s) and also contributed research papers. Research papers addressing any of the topics listed below, and possibly beyond, in connection to hybrid multi-core computing are solicited. It is expected that papers are original, correct, and are of high technical quality. Papers should not be currently in submission at any workshop/conference/journal with a published proceedings. The topics of interest include, but are not limited to, the following.
- Hybrid computing algorithms and applications
- Case studies and benchmark suites for hybrid programs
- Programming models for hybrid multi-core computing
- Issues in hybrid multi-core computing such as load balancing, synchronization
- Scalability studies, auto-tuning, or frameworks for hybrid programs
- Paradigms for hybrid multi-core computing
- Performance issues and models for hybrid multi-core computing
- Programming languages and tools for hybrid multi-core computing
The workshop seeks original, correct, and novel submissions of high quality that are not currently under review at any other venue. Submissions should not exceed eight (8) pages in the two column IEEE conference format including references, tables, and all other material. An appendix can be included but there is no guarantee that the appendix shall also be read by the reviewers. Submissions that deviate significantly from the above guidelines may not be considered. All submitted papers shall be reviewed by at least three independent reviewers before arriving at a decision.
Click here to submit your paper using EasyChair.
- Submission deadline (Extended): October 9th, 2011
- Acceptance notification: November 5th, 2011
- Camera Ready deadline: November 12th, 2011
- Workshop Date: Dec 18th, 2011
The workshop is jointly organized by IIIT Hyderabad and IBM, India.
- P. J. Narayanan, IIIT Hyderabad, India..
- Dinesh Manocha, UNC, USA
- David Kirk, Nvidia
- Kishore Kothapalli, IIIT Hyderabad, India
- Suresh Purini, IIIT Hyderabad, India
- Subodh Kumar, IIT Delhi, India
- John Owens, UC Davis, USA
- Gagan Agrawal, Ohio State, USA
- R. Govindarajan, IISc, Bangalore, India
- Mainak Chaudhari, IIT Kanpur, India
- David Bader, Georgia Tech, USA
- Bo Hong, Georgia Institue of Technology, USA
- Weng-Fai Wong, NUS, Singapore
- Philippas Tsigas, Chalmers Univeristy, Sweeden